1. Field of the Invention
The present invention relates to the field of integrated optics, more particularly to the manufacture of planar or integrated optical circuits and the alignment of optical features and devices in superposed layers of such circuits.
2. Technical Background
In the manufacture of planar or integrated optical circuits it is often necessary to create superposed layers of optical features or devices (such as waveguides, gratings, detectors, mirrors, trenches, and so forth). For example, there could be a first set of waveguides (or other optical features or physical structures) created in a first layer formed on a substrate, and a second set of different waveguides (or different optical features or physical structures) formed in a second layer, superposed on the first layer. During manufacture of such circuits, the problem arises of correctly aligning the features and devices of the upper layer with respect to those in the lower layer (or layers). This problem can be better understood from a consideration of a conventional process for manufacturing waveguides on a substrate. However, it is to be understood that this problem is not exclusive to the case where the features and devices formed on the substrate are waveguides, but applies also when other optical features and/or active or passive optoelectronic devices are concerned. FIG. 1 illustrates the steps of a typical process for forming waveguides on a substrate. FIG. 1A shows a typical substrate 1 made of silica and having a diameter of 100-150 mm.
In a first stage of the process, a first core glass layer 2, of around 6 xcexcm thickness and made of doped silica, is deposited on the substrate 1, as illustrated in FIG. 1B. Typically, the silica is doped with GeO2 (sometimes with P2O5 or B2O3 added), but other dopants can be used, for example TiO2. The doped silica is deposited by any convenient technique, for example, flame hydrolysis deposition (FHD), plasma enhanced chemical vapour deposition (PECVD), or atmospheric pressure chemical vapour deposition (APCVD).
In a second stage of the process, a mask layer 3 is formed on the core layer 2, as illustrated in FIG. 1C, by a process such as PECVD, thermal or electron-beam evaporation, or sputtering. The mask 3 layer may be made of any suitable mineral material and typically has a thickness of 0.5 to 5 xcexcm. The core layer 3 is patterned, using standard photolithography and etching processes (for example, reactive ion etching, RIE), so as to define the shapes of the cores of the waveguides which it is desired to form on the substrate, as well as alignment marks for use in subsequent processing.
In the next stage of the process, the core layer 2 is etched through the openings of the mask material by any suitable etching process (for example, RIE) to remove unwanted portions of the core layer, as illustrated in FIG. 1D. The mask material is eliminated, for example by high pressure plasma etching, to leave only the desired core pattern 2a, and alignment marks 2b,as illustrated in FIG. 1E. Then, in a final stage of the process, an overclad layer 4, typically 20 xcexcm thick and made of silica (SiO2) doped with B2O3 and/or P2O5, is deposited over the etched core patterns by a process such as FHD or APCVD, as illustrated in FIG. 1F. Although the surface of the overclad layer 4 is not usually as flat as represented in FIG. 1F, it smoothly covers the cores of the waveguides.
When it is desired to create a new pattern in a layer superposed on the overclad layer 4, aligned with the underlying patterns, there is a problem because of low contrast of the core patterns and alignment marks under the overclad. Despite the transparency of the overclad material, the underlying core patterns and alignment marks have a fuzzy aspect because of the relatively large thickness of the overclad layer 4. Moreover, the smooth topography leads to a great uncertainty as to the location of the center of the core pattern with respect to which the superposed pattern is to be aligned.
Incidentally, the conventional process could equally well have been described with reference to formation of waveguides on a silicon substrate. However, in such a case, there would be an extra step involved, namely the creation (for example, by thermal growth and PECVD) of a relatively thick ( greater than 15 xcexcm) silica underlayer interposed between the substrate and the core layer.
In order to solve the problem identified above, the present invention provides a method for forming a planar lightwave circuit or lightwave optical circuit in which one or more high-visibility alignment marks are created in a core layer. These high-visibility alignment marks enable optical features and/or devices in superposed layers to be accurately aligned with respect to the lower core pattern(s).
More particularly, the present invention provides a method of manufacturing a planar lightwave circuit or lightwave optical circuit, comprising the following steps: providing a substrate layer; forming a core layer on the substrate layer; creating a mask on the core layer, the mask being formed of a refractory material, and the mask comprising a first portion defining a first pattern and a second portion defining a second pattern, the first pattern corresponding to a desired pattern to be formed in the core layer and the second pattern corresponding to one or more alignment marks; etching the core layer through the mask whereby to expose portions of the substrate not overlaid by the first and second portions of the mask; removing the first portion of the mask whereby to expose the desired pattern in the core layer while leaving the second portion of the mask in place; forming an overclad layer on the exposed portions of the substrate, the desired pattern in the core layer and the second portion of the mask.
The present invention also provides a method of aligning optical devices in a planar lightwave circuit or lightwave optical circuit, comprising the following steps: creating a first circuit layer by providing a substrate layer, forming a core layer on the substrate layer, creating a mask on the core layer, the mask being formed of a refractory material, and the mask comprising a first portion defining a first pattern and a second portion defining a second pattern, the first pattern corresponding to a desired pattern to be formed in the core layer and the second pattern corresponding to one or more alignment marks, etching the core layer through the mask whereby to expose portions of the substrate not overlaid by the first and second portions of the mask, removing the first portion of the mask whereby to expose the desired pattern in the core layer while leaving the second portion of the mask in place, and forming an overclad layer on the exposed portions of the substrate, the desired pattern in the core layer and the second portion of the mask; and creating a second circuit layer, overlaid on the first circuit layer, the second circuit layer comprising at least one optical device located at a determined position; wherein in the step of creating the second circuit layer the position of the at least one optical device is controlled with reference to the one or more alignment marks in the first circuit layer.
The methods according to the invention provide the advantage that they create alignment marks which, because of the mask material remaining thereon, are highly visible, even through a relatively thick overclad layer (of the order of 10""s of micrometers). Moreover, because the alignment marks are formed on the substrate in the same lithography/etching steps as the core patterns on the substrate, the relative positions of the alignment marks and these core patterns are very accurately defined (auto-alignment). Indeed, the accuracy of the alignment is defined by the accuracy of the master mask and can be better than 0.1 xcexcm. Furthermore, the highly-visible alignment marks are created by a very simple process using standard processing.
In the methods according to the invention, the first mask portion can be removed from the etched core layer (while leaving the second mask portion in place) by using a specific lithography step to define an auxiliary mask shielding the second mask portion, then etching to remove the first mask portion, and removing this auxiliary mask. Alternatively, if the alignment marks are sufficiently far away from the core pattern(s), it is possible simply to cover the second portion of the mask with a polymer material, remove the first portion of the mask (for example by a plasma treatment), then remove the polymer material.
In the methods of the present invention, the mask is made of a refractory material in view of the need to withstand the high temperatures (typically 800xc2x0 C. to 1300xc2x0 C.) involved in creation of the overclad layer.
In some embodiments of the invention, the mask material may be silicon. Use of a silicon mask results in alignment marks having a highly-visible, metallic aspect. Moreover, because the silicon mask material is fully compatible with silicon and silicon dioxide layers (such as those used in the substrate and core layers) there will be no contamination of the optical layers by the mask material during the process of forming the overclad layer.
In those embodiments of the invention in which a silicon mask is used, it can be advantageous, in some circumstances, to include an additional step consisting of partially oxidising the second portion of the mask, before forming the overclad layer. This partial oxidation step creates a barrier layer which prevents an outgassing phenomenon which can sometimes occur during the formation of the overclad layer. The outgassing phenomenon consists in the emission of gas from the (amorphous) silicon mask layer, which gas could otherwise create bubbles in the overclad layer and reduce the visibility of the alignment marks. The partial oxidation step should involve subjecting the second mask portion to a temperature of around 1000xc2x0 C. for approximately at least 5 minutes in ambient atmosphere.